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DATA SHEET
MOS INTEGRATED CIRCUIT
PD703003
V853TM 32/16-BIT SINGLE-CHIP MICROCONTROLLER
The PD703003 is a member of the V850 FamilyTM of 32-bit single-chip microcontrollers designed for real-time control operations. This microcontroller provides on-chip features, including a 32-bit CPU core, ROM, RAM, interrupt controller, real-time pulse unit, a serial interface, an A/D converter, a D/A converter, and PWM signal units. See the following manuals for a detailed description of this product's functions. Be sure to use these manuals as a reference for design. V853 USER'S MANUAL, HARDWARE: V850 FAMILY USER'S MANUAL, ARCHITECTURE: U10913E U10243E
FEATURES
* Number of instructions: 74 * Minimum instruction execution time 30 ns (during 33-MHz operation) * General registers 32 bits x 32 registers * Instruction set optimized for control applications * On-chip memory ROM: 128 Kbytes RAM: 4 Kbytes
* Advanced on-chip interrupt controller * Real-time pulse unit suitable for control operations * Powerful serial interface (on-chip dedicated baud rate generator) * On-chip clock generator * 10-bit resolution A/D converter: 8 channels * 8-bit resolution D/A converter: 2 channels * 8/9/10/12-bit resolution PWM: 2 channels * Power saving functions
APPLICATIONS
* AV: Video cameras, VCRs, etc. * Office equipment: PPCs, LBPs, printers, etc. * Industrial equipment: motor controllers, NC machine tools, etc. * Communications equipment: Mobile telephones, etc.
The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. U12261EJ2V1DS00 (2nd edition) Date Published April 1999 N CP(K) Printed in Japan
The mark
shows major revised points.
(c)
1997
PD703003
ORDERING INFORMATION
Part Number Package Maximum operating frequency (MHz) 25 33
PD703003GC-25-xxx-7EA 100-pin plastic QFP (fine pitch) (14 x 14 mm) PD703003GC-33-xxx-7EA 100-pin plastic QFP (fine pitch) (14 x 14 mm)
Remark "xxx" indicates ROM code suffix.
PIN CONFIGURATION
* 100-Pin Plastic QFP (fine pitch) (14 x 14 mm)
PD703003GC-25-xxx-7EA PD703003GC-33-xxx-7EA
P30/TO130 P27/SCK1 P26/RXD1/SI1 P25/TXD1/SO1 P24/SCK0 P23/RXD0/SI0 P22/TXD0/SO0 P21/PWM1 P20/PWM0 NMI VDD VSS P17/INTP123/SCK2 P16/INTP122/SI2 P15/INTP121/SO2 P14/INTP120 P13/TI12 P12/TCLR12 P11/TO121 P10/TO120 AVDD AVSS AVREF1 P77/ANI7 P76/ANI6 P31/TO131 P32/TCLR13 P33/TI13 P34/INTP130 P35/INTP131/SO3 P36/INTP132/SI3 P37/INTP133/SCK3 P63/A19 P62/A18 P61/A17 P60/A16 VSS VDD P57/AD15 P56/AD14 P55/AD13 P54/AD12 P53/AD11 P52/AD10 P51/AD9 P50/AD8 P47/AD7 P46/AD6 P45/AD5 P44/AD4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
Caution
Connect the IC pin directly to VSS.
2
P43/AD3 P42/AD2 VSS VDD P41/AD1 P40/AD0 P90/LBEN P91/UBEN P92/R/W P93/DSTB P94/ASTB P95/HLDAK P96/HLDRQ WAIT IC MODE RESET CVDD/CKSEL X2 X1 CVSS CLKOUT VSS VDD P110/TO140
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
P75/ANI5 P74/ANI4 P73/ANI3 P72/ANI2 P71/ANI1 P70/ANI0 ANO0 ANO1 AVREF2 AVREF3 P07/INTP113/ADTRG P06/INTP112 P05/INTP111 P04/INTP110 P03/TI11 P02/TCLR11 P01/TO111 P00/TO110 P117/INTP143 P116/INTP142 P115/INTP141 P114/INTP140 P113/TI14 P112/TCLR14 P111/TO141
Data Sheet U12261EJ2V1DS00
PD703003
PIN NAMES
A16 to A19 AD0 to AD15 ADTRG ANI0 to ANI7 ANO0, ANO1 ASTB AVDD AVREF1 to AVREF3 AVSS CVDD CVSS CKSEL CLKOUT DSTB HLDAK HLDRQ IC INTP120 to INTP123, INTP130 to INTP133, INTP140 to INTP143 LBEN MODE NMI P00 to P07 P10 to P17 P20 to P27 : Lower Byte Enable : Mode : Non-maskable Interrupt Request : Port0 : Port1 : Port2 : Address Bus : Address/Data Bus : AD Trigger Input : Analog Input : Analog Output : Address Strobe : Analog VDD : Analog Reference Voltage : Analog VSS : Power Supply for Clock Generator : Ground for Clock Generator : Clock Select : Clock Output : Data Strobe : Hold Acknowledge : Hold Request : Internally Connected P30 to P37 P40 to P47 P50 to P57 P60 to P63 P70 to P77 P90 to P96 P110 to P117 PWM0, PWM1 RESET R/W RXD0, RXD1 SCK0 to SCK3 SI0 to SI3 SO0 to SO3 TO110, TO111, TO120, TO121, TO130, TO131, TO140, TO141 TCLR11 to TCLR14 : Timer Clear TI11 to TI14 TXD0, TXD1 UBEN WAIT X1, X2 VDD VSS : Timer Input : Transmit Data : Upper Byte Enable : Wait : Crystal : Power Supply : Ground : Port3 : Port4 : Port5 : Port6 : Port7 : Port9 : Port11 : Pulse Width Modulation : Reset : Read/Write Status : Receive Data : Serial Clock : Serial Input : Serial Output : Timer Output
INTP110 to INTP113, : Interrupt Request from Peripherals
Data Sheet U12261EJ2V1DS00
3
PD703003
INTERNAL BLOCK DIAGRAM
Mask ROM NMI INTP110 to INTP113 INTP120 to INTP123 INTP130 to INTP133 INTP140 to INTP143 TO110, TO111 TO120, TO121 TO130, TO131 TO140, TO141 TCLR11 to TCLR14 TI11 to TI14 SIO SO0/TXD0 SI0/RXD0 SCK0 UART0/CSI0 INTC 128 Kbytes PC
32-bit barrel shifter
CPU
Instruction queue
Multiplier 16x1632 BCU
System register
ASTB DSTB R/W UBEN LBEN WAIT A16 to A19 AD0 to AD15 HLDRQ HLDAK
RPU
RAM
General register 32 bits x 32 ALU
4 Kbytes
BRG0 SO1/TXD1 SI1/RXD1 SCK1
UART1/CSI1 BRG1
A/D converter
D/A converter
Port
P110 to P117 P90 to P96 P70 to P77 P60 to P63 P50 to P57 P40 to P47 P30 to P37 P20 to P27 P10 to P17 P00 to P07
CG
SO2 SI2 SCK2
CSI2 BRG2
ANO0, ANO1 AVREF2, AVREF3
ANI0 to ANI7 AVREF1 AVSS AVDD ADTRG
CKSEL CLKOUT X1 X2 MODE RESET VDD VSS CVDD CVSS
SO3 SI3 SCK3 PWM0, PWM1
CSI3
PWM
4
Data Sheet U12261EJ2V1DS00
PD703003
CONTENTS
1.
DIFFERENCES AMONG PRODUCTS ...........................................................................................
6 7
7 9 11
2. LIST OF PIN FUNCTIONS ...............................................................................................................
2.1 2.2 2.3 Port Pins ................................................................................................................................................ Non-port Pins ........................................................................................................................................ I/O Circuits of Pins and Processing of Unused Pins .........................................................................
3. FUNCTION BLOCKS ....................................................................................................................... 14
3.1 Internal Units ......................................................................................................................................... 14
4. CPU FUNCTIONS ............................................................................................................................ 16 5. BUS CONTROL FUNCTIONS ......................................................................................................... 17 6. INTERRUPT/EXCEPTION HANDLING FUNCTIONS ..................................................................... 18 7. CLOCK GENERATION FUNCTIONS .............................................................................................. 21 8. TIMER/COUNTER FUNCTIONS (REAL-TIME PULSE UNIT) ........................................................ 22 9. SERIAL INTERFACE FUNCTIONS (SIO) ....................................................................................... 24
9.1 9.2 9.3 Asynchronous Serial Interface 0, 1 (UART0, UART1) ........................................................................ Clock-synchronized Serial Interface 0 to 3 (CSI0 to CSI3) ................................................................ Baud Rate Generator 0 to 2 (BRG0 to BRG2) ..................................................................................... 24 26 28
10. PWM UNIT ....................................................................................................................................... 29 11. A/D CONVERTER ............................................................................................................................ 30 12. D/A CONVERTER ............................................................................................................................ 31 13. PORT FUNCTIONS .......................................................................................................................... 32 14. RESET FUNCTIONS ........................................................................................................................ 45 15. INSTRUCTION SET ......................................................................................................................... 46 16. ELECTRICAL SPECIFICATIONS .................................................................................................... 53 17. PACKAGE DRAWINGS ................................................................................................................... 77 18. RECOMMENDED SOLDERING CONDITIONS ............................................................................... 78
Data Sheet U12261EJ2V1DS00
5
PD703003
1. DIFFERENCES AMONG PRODUCTS
Item Internal ROM
PD703003 PD703003A PD703004A PD703025A PD70F3003 PD70F3003A PD70F3025A
Mask ROM 128 Kbytes 96 Kbytes Flash memory 256 Kbytes 128 Kbytes 8 Kbytes 4 Kbytes 256 Kbytes 8 Kbytes
Internal RAM Operation Normal mode operation mode
4 Kbytes Single-chip Implemented mode ROM-less mode Implemented Not implemented
Implemented Not implemented
Flash memory programming mode VPP pin
Not implemented
Implemented
Not implemented MODE = 0 : 03H MODE = 1 : 00H
Implemented 00H MODE = 0 : 03H MODE = 1 : 00H
Value of CKC register when reset 00H
Electrical specifications Others
Power consumption levels vary (see specific product's data sheet). Noise tolerance and noise emission vary, depending on the circuit scale and mask layout.
6
Data Sheet U12261EJ2V1DS00
PD703003
2. LIST OF PIN FUNCTIONS
2.1 Port Pins (1/2)
Pin Name P00 P01 P02 P03 P04 P05 P06 P07 P10 P11 P12 P13 P14 P15 P16 P17 P20 P21 P22 P23 P24 P25 P26 P27 P30 P31 P32 P33 P34 P35 P36 P37 P40 to P47 I/O Port 4 8-bit I/O port Input/output mode can be specified bitwise P50 to P57 I/O Port 5 8-bit I/O port Input/output mode can be specified bitwise AD8 to AD15 I/O Port 3 8-bit I/O port Input/output mode can be specified bitwise I/O Port 2 8-bit I/O port Input/output mode can be specified bitwise I/O Port 1 8-bit I/O port Input/output mode can be specified bitwise I/O I/O Port 0 8-bit I/O port Input/output mode can be specified bitwise Function Alternate Function Pin TO110 TO111 TCLR11 TI11 INTP110 INTP111 INTP112 INTP113/ADTRG TO120 TO121 TCLR12 TI12 INTP120 INTP121/SO2 INTP122/SI2 INTP123/SCK2 PWM0 PWM1 TXD0/SO0 RXD0/SI0 SCK0 TXD1/SO1 RXD1/SI1 SCK1 TO130 TO131 TCLR13 TI13 INTP130 INTP131/SO3 INTP132/SI3 INTP133/SCK3 AD0 to AD7
Data Sheet U12261EJ2V1DS00
7
PD703003
(2/2)
Pin Name P60 to P63 I/O I/O Port 6 4-bit I/O port Input/output mode can be specified bitwise P70 to P77 Input Port 7 8-bit input port P90 P91 P92 P93 P94 P95 P96 P110 P111 P112 P113 P114 P115 P116 P117 I/O Port 11 8-bit I/O port Input/output mode can be specified bitwise I/O Port 9 7-bit I/O port Input/output mode can be specified bitwise LBEN UBEN R/W DSTB ASTB HLDAK HLDRQ TO140 TO141 TCLR14 TI14 INTP140 INTP141 INTP142 INTP143 ANI0 to ANI7 Function Alternate Function Pin A16 to A19
8
Data Sheet U12261EJ2V1DS00
PD703003
2.2 Non-port Pins (1/2)
Pin Name TO110 TO111 TO120 TO121 TO130 TO131 TO140 TO141 TCLR11 TCLR12 TCLR13 TCLR14 TI11 TI12 TI13 TI14 INTP110 INTP111 INTP112 INTP113 INTP120 INTP121 INTP122 INTP123 INTP130 INTP131 INTP132 INTP133 INTP140 INTP141 INTP142 INTP143 SO0 SO1 SO2 SO3 SI0 SI1 SI2 SI3 Input Serial receive data input (3-wire) for CSI0 to CSI3 Output Serial transmit data output (3-wire) for CSI0 to CSI3 Input External maskable interrupt request input, shared as external capture trigger input for timer 14 Input External maskable interrupt request input, shared as external capture trigger input for timer 13 Input External maskable interrupt request input, shared as external capture trigger input for timer 12 Input External maskable interrupt request input, shared as external capture trigger input for timer 11 Input External count clock input for timers 11 to 14 Input External clear signal input for timers 11 to 14 I/O Output Function Pulse signal output from timers 11 to 14 Alternate Function Pin P00 P01 P10 P11 P30 P31 P110 P111 P02 P12 P32 P112 P03 P13 P33 P113 P04 P05 P06 P07/ADTRG P14 P15/SO2 P16/SI2 P17/SCK2 P34 P35/SO3 P36/SI3 P37/SCK3 P114 P115 P116 P117 P22/TXD0 P25/TXD1 P15/INTP121 P35/INTP131 P23/RXD0 P26/RXD1 P16/INTP122 P36/INTP132
Data Sheet U12261EJ2V1DS00
9
PD703003
(2/2)
Pin Name SCK0 SCK1 SCK2 SCK3 TXD0 TXD1 RXD0 RXD1 PWM0 PWM1 AD0 to AD7 AD8 to AD15 A16 to A19 LBEN UBEN R/W DSTB ASTB HLDAK HLDRQ ANI0 to ANI7 ANO0, ANO1 NMI CLKOUT CKSEL WAIT MODE RESET X1 X2 ADTRG AVREF1 AVREF2 AVREF3 AVDD AVSS CVDD CVSS VDD VSS IC -- -- -- -- -- -- -- Positive power supply for A/D converter Ground potential for A/D converter Positive power supply for on-chip clock generator Ground potential for on-chip clock generator Positive power supply Ground potential Internally connected pin (connect directly to VSS) CKSEL -- -- -- -- Output Input Input Output Input Output Input Input Input Input Input -- Input Input Input Output Output Output High-order address bus used for external memory expansion External data bus's low-order byte enable signal output External data bus's high-order byte enable signal output External read/write status output External data strobe signal output External address strobe signal output Bus hold acknowledge output Bus hold request input Analog input to A/D converter Analog output to D/A converter Nonmaskable interrupt request input System clock output Input for specifying clock generator's operation mode Control signal input for inserting wait in bus cycle Operation mode select System reset input Oscillator connection for system clock. Input is via X1 when using an external clock. A/D converter external trigger input Reference voltage input for A/D converter Reference voltage input for D/A converter CVDD -- -- -- -- -- P07/INTP113 -- -- -- -- -- I/O 16-bit multiplexed address/data bus for external memory expansion Output PWM pulse signal output Input Serial receive data input for UART0 and UART1 Output Serial transmit data output for UART0 and UART1 I/O I/O Function Serial clock I/O (3-wire) for CSI0 to CSI3 Alternate Function Pin P24 P27 P17/INTP123 P37/INTP133 P22/SO0 P25/SO1 P23/SI0 P26/SI1 P20 P21 P40 to P47 P50 to P57 P60 to P63 P90 P91 P92 P93 P94 P95 P96 P70 to P77 -- -- --
10
Data Sheet U12261EJ2V1DS00
PD703003
2.3 I/O Circuits of Pins and Processing of Unused Pins Table 2-1 lists I/O circuit type of respective pins and processing method (recommended connection method) when not used. Figure 2-1 illustrates the various circuit types using partially abridged diagrams. When connecting to VDD or VSS via a resistor, a resistance value in the range of 1 to 10 k is recommended. Table 2-1. I/O Circuits of Pins and Processing of Unused Pins (1/2)
Pin P00/TO110, P01/TO111 P02/TCLR11, P03/TI11, P04/INTP110 to P07/INTP113/ADTRG P10/TO120, P11/TO121 P12/TCLR12, P13/TI12 P14/INTP120 P15/INTP121/SO2 P16/INTP122/SI2 P17/INTP123/SCK2 P20/PWM0, P21/PWM1 P22/TXD0/SO0 P23/RXD0/SI0, P24/SCK0 P25/TXD1/SO1 P26/RXD1/SI1, P27/SCK1 P30/TO130, P31/TO131 P32/TCLR13, P33/TI13 P34/INTP130 P35/INTP131/SO3 P36/INTP132/SI3 P37/INTP133/SCK3 P40/AD0 to P47/AD7 P50/AD8 to P57/AD15 P60/A16 to P63/A19 P70/ANI0 to P77/ANI7 P90/LBEN P91/UBEN P92/R/W P93/DSTB P94/ASTB P95/HLDAK P96/HLDRQ P110/TO140, P111/TO141 P112/TCLR14, P113/TI14 P114/INTP140 to P117/INTP143 ANO0, ANO1 NMI 8 9 5 Connect directly to VSS Input: Connect to VDD or VSS separately via a resistor Output: Leave open 5 10-A 8 5 8 5 8 I/O Circuit Type 5 8 Recommended Connection Method Input: Connect to VDD or VSS separately via a resistor Output: Leave open
5 8
5
12 2
Leave open Connect directly to VSS
Data Sheet U12261EJ2V1DS00
11
PD703003
Table 2-1. I/O Circuits of Pins and Processing of Unused Pins (2/2)
Pin CLKOUT WAIT MODE RESET CVDD/CKSEL AVREF1 to AVREF3, AVSS AVDD IC -- -- -- Connect directly to VSS Connect directly to VDD Connect directly to VSS I/O Circuit Type 3 1 2 Leave open Connect directly to VDD -- Recommended Connection Method
12
Data Sheet U12261EJ2V1DS00
PD703003
Figure 2-1. I/O Circuits of Pins
Type 1
Type 8
VDD P-ch IN/OUT
VDD P-ch IN N-ch
Data
Output disable
N-ch
Type 2
Type 9
P-ch IN IN N-ch
+ -
Comparator
VREF (threshold voltage)
Input enable Schmitt trigger input with hysteresis characteristics Type 3 Type 10-A VDD
VDD P-ch OUT N-ch
Pull-up enable Data
P-ch VDD P-ch IN/OUT
Open-drain output disable
N-ch
Type 5 VDD Data P-ch IN/OUT Output disable N-ch
Type 12
Analog output voltage
P-ch N-ch
OUT
Input enable
Data Sheet U12261EJ2V1DS00
13
PD703003
3. FUNCTION BLOCKS
3.1 Internal Units 3.1.1 CPU The CPU uses five-stage pipeline control to enable single-clock execution of address calculations, arithmetic logic operations, data transfers, and almost all other instruction processing. Other dedicated on-chip hardware, such as the multiplier (16 bits x 16 bits) and the barrel shifter (32 bits) help accelerate processing of complex instructions. 3.1.2 Bus control unit (BCU) The BCU starts a required bus cycle based on the physical address obtained by the CPU. When an instruction is fetched from external memory space and the CPU does not send a bus cycle start request, the BCU generates a prefetch address and prefetches the instruction code. The prefetched instruction code is stored in a prefetch queue. 3.1.3 ROM ROM is mapped to the address space starting at 00000000H. The MODE pin can be used to select an access enable/disable setting. ROM can be accessed by the CPU in one clock cycle when an instruction is fetched. 3.1.4 RAM RAM is mapped to the address space starting at FFFFE000H. RAM can be accessed by the CPU in one clock cycle when data accessed. 3.1.5 Ports In addition to the 75 pins (port 0 to port 11) comprising I/O ports (of which eight pins comprise an input-only port), various port pin and control pin functions can be selected for these pins. 3.1.6 Interrupt controller (INTC) This controller handles hardware interrupt requests (NMI, INTP110 to INTP113, INTP120 to INTP123, INTP130 to INTP133, and INTP140 to INTP143) from on-chip peripheral hardware and external hardware. Eight interrupt priority levels can be specified for these interrupt requests, and multiplexed servicing control can be performed for interrupt sources. 3.1.7 Clock generator (CG) An on-chip PLL enables the CPU operating clock to be supplied to resonators connected to pins X1 and X2 at 5x frequency, 1x frequency, and 1/2x frequency. It can also be connected to an external clock instead of to the resonator. 3.1.8 Real-time pulse unit (RPU) The RPU includes a four-channel 16-bit timer/event counter and a one-channel 16-bit interval timer, which enables measurement of pulse intervals and frequency as well as programmable pulse output.
14
Data Sheet U12261EJ2V1DS00
PD703003
3.1.9 Serial interface (SIO) Four channels are comprised of two kinds of serial interfaces: an asynchronous serial interface (UART) and a clocksynchronized serial interface (CSI). Two of these four channels are switchable between the UART and CSI and the other two channels are fixed as CSI. For UART, data is transferred via the TXD and RXD pins. The baud rate is determined by the on-chip baud rate generator. For CSI, data is transferred via the SO, SI, and SCK pins. The baud rate can be determined by the onchip baud rate generator or it can be supplied from an external source. One of the two CSI-fixed channels is used as the serial clock output, and serial output is sent via an N-ch open drain output. 3.1.10 Pulse width modulation (PWM) There are two channels of selectable 8/9/10/12-bit resolution PWM signal outputs. When a low pass filter is externally connected, PWM output can be used as D/A converter output. This is suitable for actuator control applications, such as in motors. 3.1.11 A/D converter (ADC) This is a high-speed, high-resolution 10-bit A/D converter that includes eight analog input pins. It converts using the sequential conversion method. 3.1.12 D/A converter (DAC) This is an 8-bit resolution D/A converter that includes two channels. It converts using the R-2R conversion method.
Data Sheet U12261EJ2V1DS00
15
PD703003
4. CPU FUNCTIONS
The CPU employs a RISC-based architecture and uses five-stage pipeline control to enable single-clock execution of almost all instructions. The features of the CPU functions are shown below. * Minimum instruction execution time 30 ns (during internal 33-MHz operation) * Address space: 16-Mbyte linear * General registers: 32 bits x 32 registers * Internal 32-bit architecture * 5-stage pipeline control * Multiply/divide instructions * Saturated operation instructions * 32-bit shift instruction: 1 clock * Long/short format * Four types of bit manipulation instructions * Set * Clear * Not * Test
16
Data Sheet U12261EJ2V1DS00
PD703003
5. BUS CONTROL FUNCTIONS
The features of the bus control functions are shown below. * Shared as port pins, connectable to external device * Wait functions * Programmable wait function for up to three states per two blocks * External wait function using WAIT pin * Idle state insertion function * Bus mastering arbitration function * Bus hold function
Data Sheet U12261EJ2V1DS00
17
PD703003
6. INTERRUPT/EXCEPTION HANDLING FUNCTIONS
The features of the interrupt/exception handling functions are shown below. * Interrupts * Nonmaskable interrupt: 1 source * Maskable interrupt: 32 sources * 8-level programmable priority control * Multiple interrupt control based on priority levels * Mask specification for each maskable interrupt request * Noise elimination, edge detection, and valid edge specification for external interrupt requests * Exceptions * Software exceptions: 32 sources * Exception trap: 1 source (invalid instruction code exception) The configuration of the interrupt/exception handling functions is shown below. Figure 6-1. Block Diagram of Maskable Interrupt
Internal bus 7 XXMKn (interrupt mask flag)
INTOV11 INTOV12 INTOV13 INTOV14 INTP110/INTCC110 INTP111/INTCC111 INTP112/INTCC112 INTP113/INTCC113 INTP120/INTCC120 INTP121/INTCC121 INTP122/INTCC122 INTP123/INTCC123 INTP130/INTCC130 INTP131/INTCC131 INTP132/INTCC132 INTP133/INTCC133 INTP140/INTCC140 INTP141/INTCC141 INTP142/INTCC142 INTP143/INTCC143 INTCM4 OVIF11 OVIF12 OVIF13 OVIF14 P11IF0 P11IF1 P11IF2 P11IF3 P12IF0 P12IF1 P12IF2 P12IF3 P13IF0 P13IF1 P13IF2 P13IF3 P14IF0 P14IF1 P14IF2 P14IF3 CMIF4 CSIF0 CSIF1 CSIF2 CSIF3 SEIF0 SRIF0 STIF0 SEIF1 SRIF1 STIF1 ADIF
0 ISPR
3210321032103210
3210321032103210
RPU
Handler address generator
XXPRn (priority controller)
INTP110 INTP111 INTP112 INTP113 INTP120 INTP121 INTP122 INTP123 INTP130 INTP131 INTP132 INTP133 INTP140 INTP141 INTP142 INTP143
INTM1 INTM2 INTM3 INTM4
3210 321032103210
Selector
Interrupt request Interrupt request acknowledge HALT mode release signal
CPU
SIO
INTCSI0 INTCSI1 INTCSI2 INTCSI3 INTSER0 INTSR0 INTST0 INTSER1 INTSR1 INTST1
PSW ID
A/D converter
INTAD
XX: Name of peripheral unit (OV, P11 to P14, CM, CS, SE, SR, ST, AD) n: Peripheral unit number (if none exists, then 0 to 4 or 11 to 14)
18
Data Sheet U12261EJ2V1DS00
PD703003
Interrupt/exception sources are shown in Table 6-1. Table 6-1. List of Interrupts (1/2)
Interrupt/Exception Source Type Category Name Control Register -- -- -- -- -- Trigger Source Unit Default Priority Level Reset input NMI input TRAP instruction TRAP instruction Undefined instruction code -- -- -- -- -- RPU RPU RPU RPU Pin/RPU Pin/RPU Pin/RPU Pin/RPU Pin/RPU Pin/RPU Pin/RPU Pin/RPU Pin/RPU Pin/RPU Pin/RPU Pin/RPU Pin/RPU Pin/RPU Pin/RPU Pin/RPU RPU SIO SIO SIO -- -- -- -- -- 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
Exception Code 0000H 0010H 004nHNote 005nHNote 0060H 0080H 0090H 00A0H 00B0H 00C0H 00D0H 00E0H 00F0H 0100H 0110H 0120H 0130H 0140H 0150H 0160H 0170H 0180H 0190H 01A0H 01B0H 01C0H 01D0H 01E0H 01F0H
Handler Restored Address 00000000H 00000010H 00000040H 00000050H 00000060H 00000080H 00000090H PC Undefined nextPC nextPC nextPC nextPC nextPC nextPC
Reset
Interrupt
RESET NMI TRAP0nNote TRAP1nNote
Nonmaskable Interrupt Software exception Exception trap Maskable Exception Exception
Exception ILGOP Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt INTOV11 INTOV12 INTOV13 INTOV14
OVIC11 Timer 11 overflow OVIC12 Timer 12 overflow OVIC13 Timer 13 overflow OVIC14 Timer 14 overflow Match between INTP110 and CC110 Match between INTP111 and CC111 Match between INTP112 and CC112 Match between INTP113 and CC113 Match between INTP120 and CC120 Match between INTP121 and CC121 Match between INTP122 and CC122 Match between INTP123 and CC123 Match between INTP130 and CC130 Match between INTP131 and CC131 Match between INTP132 and CC132 Match between INTP133 and CC133 Match between INTP140 and CC140 Match between INTP141 and CC141 Match between INTP142 and CC142 Match between INTP143 and CC143 Signal matches CM4 CSI0 send/receive completion CSI1 send/receive completion CSI2 send/receive completion
000000A0H nextPC 000000B0H nextPC 000000C0H nextPC 000000D0H nextPC 000000E0H nextPC 000000F0H nextPC 00000100H 00000110H 00000120H 00000130H 00000140H 00000150H 00000160H 00000170H 00000180H 00000190H nextPC nextPC nextPC nextPC nextPC nextPC nextPC nextPC nextPC nextPC
INTP110/INTCC110 P11IC0 INTP111/INTCC111 P11IC1 INTP112/INTCC112 P11IC2 INTP113/INTCC113 P11IC3 INTP120/INTCC120 P12IC0 INTP121/INTCC121 P12IC1 INTP122/INTCC122 P12IC2 INTP123/INTCC123 P12IC3 INTP130/INTCC130 P13IC0 INTP131/INTCC131 P13IC1 INTP132/INTCC132 P13IC2 INTP133/INTCC133 P13IC3 INTP140/INTCC140 P14IC0 INTP141/INTCC141 P14IC1 INTP142/INTCC142 P14IC2 INTP143/INTCC143 P14IC3 INTCM4 INTCSI0 INTCSI1 INTCSI2 CMIC4 CSIC0 CSIC1 CSIC2
000001A0H nextPC 000001B0H nextPC 000001C0H nextPC 000001D0H nextPC 000001E0H nextPC 000001F0H nextPC
Note n represents a value between 0 and FH. Remarks 1. Default priority: The default priority level is the level that takes precedence when multiple maskable interrupt requests having the same priority level occur at the same time. The highest priority level is level 0. Restored PC: This is the PC value that is saved to EIPC or FEPC when interrupt or exception handling is activated. However, if an interrupt occurs during execution of the DIVH (divide) instruction, the recovered PC value is the PC value of the current instruction (DIVH). 2. The invalid instruction execution address can be obtained (using restored PC-4) when an invalid instruction code exception occurs.
Data Sheet U12261EJ2V1DS00
19
PD703003
Table 6-1. List of Interrupts (2/2)
Interrupt/Exception Source Type Category Name Control Register CSIC3 SEIC0 SRIC0 STIC0 SEIC1 SRIC1 STIC1 ADIC Trigger Source Unit Default Priority Level CSI3 transmit/receive completion UART0 receive error UART0 receive completion UART0 transmit completion UART1 receive error UART1 receive completion UART1 transmit completion A/D conversion completion SIO SIO SIO SIO SIO SIO SIO ADC 24 25 26 27 28 29 30 31
Exception Code 0200H 0210H 0220H 0230H 0240H 0250H 0260H 0270H
Handler Address 00000200H 00000210H 00000220H 00000230H 00000240H 00000250H 00000260H 00000270H
Restored PC nextPC nextPC nextPC nextPC nextPC nextPC nextPC nextPC
Maskable
Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt
INTCSI3 INTSER0 INTSR0 INTST0 INTSER1 INTSR1 INTST1 INTAD
Remarks 1. Default priority: The default priority level is the level that takes precedence when multiple maskable interrupt requests having the same priority level occur at the same time. The highest priority level is level 0. Restored PC: This is the PC value that is saved to EIPC or FEPC when interrupt or exception handling is started. However, if an interrupt occurs during execution of the DIVH (divide) instruction, the restored PC value is the PC value of the current instruction (DIVH). 2. The invalid instruction execution address can be obtained using (restored PC-4) when an invalid instruction code exception occurs.
20
Data Sheet U12261EJ2V1DS00
PD703003
7. CLOCK GENERATION FUNCTIONS
The features of the clock generation functions are shown below. * Multiplier function using PLL clock synthesizer * Clock sources * Oscillation via resonator connection (PLL mode): fXX = , 2 x , /5 * External clock (PLL mode): fXX = , 2 x , /5 * External clock (direct mode): fXX = 2 x * Power saving control * HALT mode * IDLE mode * Software STOP mode * Clock output inhibit mode The configuration of the clock generation functions is shown below. Figure 7-1. Block Diagram of Clock Generation Functions
X1 (fXX) X2 Clock generator
CPU, On-chip peripheral I/O
CLKOUT
CKSEL
Remark : internal system clock
Data Sheet U12261EJ2V1DS00
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PD703003
8. TIMER/COUNTER FUNCTIONS (REAL-TIME PULSE UNIT)
The features of the timer/counter functions are shown below. * Measurement of pulse interval and frequency, programmable pulse output * 16-bit measurements enabled * Generates a variety of pulse patterns (interval pulse, one-shot pulse, etc.) * Timer 1 * 16-bit timer/event counter * Count clock sources: two types (selection of an internal system clock division, external pulse input) * Capture/compare (shared) registers: 16 * Count clear pins: TCLR11 to TCLR14 * Interrupt sources: 20 types * External pulse outputs: 8 * Timer 4 * 16-bit interval timer * Count clock: selected from an internal system clock division * Compare register: 1 * Interrupt sources: 1
22
Data Sheet U12261EJ2V1DS00
PD703003
The configurations of the timer/counter functions are shown below. Figure 8-1. Block Diagram of Timer 1 (16-bit timer/event counter)
TCLR1n
Edge detect
Clear and start Clear and start
/2 /4
m
m m/4 m/8 m/32
Note 2
Note 1
TM1n (16 bits)
INTOV1n
TI1n
Edge detect
INTCC1n0 INTCC1n1 CC1n0 CC1n1 CC1n2 CC1n3 S R S
Note3
INTP1n0 INTP1n1 INTP1n2 INTP1n3
Edge detect Edge detect Edge detect Edge detect
Q TO1n0 Q
Q TO1n1
RNote3 Q INTCC1n2 INTCC1n3
Notes 1. Internal count clock 2. External count clock 3. Priority to reset Remark : internal system clock n = 1 to 4 Figure 8-2. Block Diagram of Timer 4 (16-bit interval timer)
/2 /4 m /16 /32
Note m m/32
TM4 (16-bit)
Clear and start
CM4
INTCM4
Note Internal count clock Remark : Internal system clock
Data Sheet U12261EJ2V1DS00
23
PD703003
9. SERIAL INTERFACE FUNCTIONS (SIO)
Two types and six channels of serial interfaces are provided. Up to four channels may be used at the same time. (1) Asynchronous serial interfaces 0, 1 (UART0, UART1): 2 channels (2) Clock-synchronized serial interfaces 0 to 3 (CSI0 to CSI3): 4 channels Caution UART0 and CSI0 are a shared pin, as are UART1 and CSI1. Either one can be selected via a register (ASIM00, ASIM10). 9.1 Asynchronous Serial Interfaces 0, 1 (UART0, UART1) The features of the asynchronous serial interfaces 0, 1 (UART0, UART1) are shown below. * Transfer rate 150 bps to 76800 bps (@ = 33-MHz operation, using baud rate generator) 110 bps to 307200 bps (@ = 20-MHz operation, using baud rate generator) Maximum 1031 Kbytes (@ = 33-MHz operation, using /2) * Full duplex communications: Receive buffer (RXBn) included * Two-pin configuration TXDn: output pin for transmit data RXDn: input pin for receive data * Reception error detection function * Parity error * Framing error * Overrun error * Three types of interrupt sources * Reception error interrupt (INTSERn) * Reception completion interrupt (INTSRn) * Transmission completion interrupt (INTSTn) * The character length of transmit and receive data is specified via the ASIMn0, ASIMn1 register * Character lengths: 7 or 8 bits, or 9 bits (if using expansion bit) * Parity function: even, odd, zero, or no parity * Transmission stop bits: 1 or 2 bits * On-chip baud rate generator Remark n = 0, 1
: internal system clock
24
Data Sheet U12261EJ2V1DS00
PD703003
The configuration of the asynchronous serial interfaces 0, 1 (UART0, UART1) are shown below. Figure 9-1. Block Diagram of Asynchronous Serial Interfaces 0, 1 (UART0, UART1)
Internal bus 16/8
Receive buffer
8 ASIMn0 RXBn RXBnL 8 ASISn 16/8
TXEn RXEn PSn1 PSn0 CLn SLn SCLSn
8 ASIMn1 EBSn
RXDn TXDn
Receive shift register
PEn FEn OVEn SOTn
Transmit TXSn shift register TXSnL
Reception control parity check
INTSRn
Transmission INTSERn control parity attachment
INTSTn
1 2
Selector
1 16
1 16
Baud rate generator
Remark n = 0, 1
: internal system clock
Data Sheet U12261EJ2V1DS00
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PD703003
9.2 Clock-synchronized Serial Interfaces 0 to 3 (CSI0 to CSI3) The features of the clock-synchronized serial interfaces 0 to 3 (CSI0 to CSI3) are shown below. * Number of channels: 4 channels (CSIn) * High-speed transfer MAX 8.25 Mbps (@ = 33-MHz operation) * Half-duplex communications * Character length uses 8-bit unit * Switchable byte ordering (MSB first or LSB first) * Selectable external serial clock input/internal serial clock output * 3-wire type SOn: Serial data output SIn: Serial data input SCKn: Serial clock I/O * Interrupt source: 1 type * Transmission/reception completion interrupt (INTCSIn)
Remark n = 0 to 3
: internal system clock
26
Data Sheet U12261EJ2V1DS00
PD703003
The configuration of the clock-synchronized serial interfaces 0 to 3 (CSI0 to CSI3) is shown below. Figure 9-2. Block Diagram of Clock-synchronized Serial Interfaces 0 to 3 (CSI0 to CSI3)
Internal bus
CSIMn
CTXEn CRXEn CSOTn MODn CLSn1 CLSn0
SO latch SIn Shift register (SIOn) D Q
SOn SCKn
Note
Selector
Note
Serial clock control circuit
Selector
1 2
Baud rate generator /2
Serial clock counter
Interrupt control circuit
INTCSIn
Note
SO0 to SO2, SCK0 to SCK2: CMOS outputs SO3, SCK3: N-ch open-drain outputs
Remark n = 0 to 3
: internal system clock
Data Sheet U12261EJ2V1DS00
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PD703003
9.3 Baud Rate Generators 0 to 2 (BRG0 to BRG2) The features of the baud rate generators 0 to 2 (BRG0 to BRG2) are shown below. * Serial clock can be selected via baud rate generator output and (internal system clock) * Identical baud rates during transmission and reception The configuration of the baud rate generators 0 to 2 (BRG0 to BRG2) is shown below. Figure 9-3. Block Diagram of Baud Rate Generators 0 to 2 (BRG0 to BRG2)
Baud rate generator 0
BPRM0
BRCE0 BPR02 BPR01
BRG0 Match Clear TMBRG0
BPR00
UART0
1 2
UART1 Baud rate generator 1 CSI1
CSI2 Baud rate generator 2 CSI3
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Data Sheet U12261EJ2V1DS00
Internal bus
CSI0
Prescaler
PD703003
10. PWM UNIT
The features of the PWM unit are shown below. * PWMn: 2 channels * Selectable active level for PWMn output pulse * Operating clock selectable as , /2, /4, /8, or /16 ( : internal system clock) * PWMn output resolution selectable as 8, 9, 10, or 12 bits Remark n = 0, 1 The configuration of the PWM unit is shown below. Figure 10-1. Block Diagram of PWM Unit
7 8
/2 /4 /8 /16
9 TMPn (12 bits) 11 0-7 0-8 0-9 Comparator 0-11
Overflow
ALVn
S Match
Q PWMn
RNote
CMPn (12 bits)
PWMn (12 bits)
Note Priority to reset Remark n = 0, 1
: internal system clock
Data Sheet U12261EJ2V1DS00
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PD703003
11. A/D CONVERTER
The features of the A/D converter are shown below. * Analog inputs: 8 channels * On-chip 10-bit A/D converter * On-chip A/D conversion result registers (ADCR0 to ADCR7) 10 bits x 8 registers * A/D conversion trigger modes A/D trigger mode Timer trigger mode External trigger mode * Sequential conversion method The configuration of the A/D converter is shown below. Figure 11-1. Block Diagram of A/D Converter
Series resistor string ANI0 ANI1
Input circuit
Sample & hold circuit
Tap selector
R/2 R
AVREF1
ANI2 ANI3 ANI4 ANI5 ANI6 ANI7
R/2
AVSS AVDD
Voltage comparator 9 SAR (10) 0 10
10 INTAD INTCC110 INTCC111 INTCC112 INTCC113 ADTRG
Noise Edge elimination detection
9 ADCR0 Controller ADCR1 ADCR2 ADCR3 ADCR4 ADCR5 7 ADM0 (8) 0 7 ADM1 (8) 0 ADCR6 ADCR7 10
0
8
8
Internal bus
30
Data Sheet U12261EJ2V1DS00
PD703003
12. D/A CONVERTER
The features of the D/A converter are shown below. * 8-bit resolution D/A converter: 2 channels * R-2R conversion method The configuration of the D/A converter is shown below. Figure 12-1. Block Diagram of D/A Converter
2R AVREF2 R 2R ANOn
Selector 2R R
2R AVREF3
DACSn
DACEn
Internal bus
Remark n = 0, 1
Data Sheet U12261EJ2V1DS00
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PD703003
13. PORT FUNCTIONS
The features of the port functions are shown below. * Number of ports Input-only ports: I/O ports: 8 67
* Alternated as I/O pins for other peripheral functions * I/O setting can be specified bitwise * Noise elimination * Edge detection The configurations of the port functions are shown below. Figure 13-1. Block Diagram of P00 and P01 (Port 0)
WRPMC PMC0n WRPM PM0n
Internal bus
WRPORT
TO11n P0n
Selector
P0n
Selector
RDIN
Address
Remark n = 0, 1
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Data Sheet U12261EJ2V1DS00
Selector
PD703003
Figure 13-2. Block Diagram of P02 to P07 (Port 0)
WRPMC PMC0n WRPM PM0n
Internal bus
WRPORT P0n P0n
Selector
RDIN INTP110-INTP112, INTP113/ADTRG, TCLR11, TI11
Noise elimination Edge detection
Address
Remark n = 2 to 7 Figure 13-3. Block Diagram of P10 and P11 (Port 1)
WRPMC PMC1n
WRPM PM1n
Internal bus
WRPORT P1n
Selector
TO12n
Selector
P1n
Selector
RDIN
Address
Remark n = 0, 1
Selector
Data Sheet U12261EJ2V1DS00
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PD703003
Figure 13-4. Block Diagram of P12 to P14 (Port 1)
WRPMC PMC1n WRPM PM1n
Internal bus
WRPORT P1n P1n
Selector
RDIN TCLR12, TI12 INTP120
Address
Noise elimination Edge detection
Remark n = 2 to 4 Figure 13-5. Block Diagram of P15 (Port 1)
PCM1 PMC15 WRPM PM15 Internal bus
WRPMC
SO2 P15
Selector
WRPORT
Selector
P15
Selector
RDIN INTP121
Address
Noise elimination Edge detection
Selector
PCM1
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Data Sheet U12261EJ2V1DS00
PD703003
Figure 13-6. Block Diagram of P16 (Port 1)
WRPMC PMC16 WRPM PM16
Internal bus
WRPORT P16
Selector Selector
P16
RDIN INTP122
Address
Noise elimination Edge detection
SI2
PCM1
Figure 13-7. Block Diagram of P17 (Port 1)
WRPMC PMC17 WRPM PM17
Internal bus
PCM1
SCK2 I/O switch
SCK2 output P17
Selector
WRPORT
P17
Selector
RDIN INTP123
Address
Noise elimination Edge detection
SCK2 output
Selector
PCM1
Data Sheet U12261EJ2V1DS00
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PD703003
Figure 13-8. Block Diagram of P20 and P21 (Port 2)
WRPMC PMC2n WRPM PM2n
Internal bus
PWM0, PWM1 P2n
Selector
WRPORT
P2n
Selector
RDIN Address
Remark n = 0, 1 Figure 13-9. Block Diagram of P22 and P25 (Port 2)
SO0, SO1 output enable PMC2n WRPM PM2n
WRPMC
Internal bus
Selector
WRPORT
TXD0/SO0 TXD1/SO1 P2n
Selector
P2n
Selector
RDIN Address
Remark n = 2, 5
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Data Sheet U12261EJ2V1DS00
Selector
PD703003
Figure 13-10. Block Diagram of P23 and P26 (Port 2)
WRPMC PMC2n WRPM PM2n
Internal bus
WRPORT P2n
Selector
P2n
RDIN
Address RXD0/SI0 RXD1/SI1
Remark n = 3, 6 Figure 13-11. Block Diagram of P24 and P27 (Port 2)
SCK0, SCK1 I/O switch
WRPMC PMC2n WRPM PM2n Internal bus
Selector
WRPORT
SCK0 output SCK1 output P2n
Selector
P2n
Selector
RDIN
Address SCK0 input SCK1 input
Remark n = 4, 7
Selector
Data Sheet U12261EJ2V1DS00
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PD703003
Figure 13-12. Block Diagram of P30 and P31 (Port 3)
WRPMC PMC3n WRPM PM3n
Internal bus
WRPORT
TO13n P3n
Selector
P3n
Selector
RDIN
Address
Remark n = 0, 1 Figure 13-13. Block Diagram of P32 to P34 (Port 3)
WRPMC PMC3n WRPM PM3n
Internal bus
WRPORT P3n
Selector
Selector
P3n
RDIN TCLR13, TI13 INTP130
Address
Noise elimination Edge detection
Remark n = 2 to 4
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Data Sheet U12261EJ2V1DS00
Selector
PD703003
Figure 13-14. Block Diagram of P35 (Port 3)
SO3 output enable PUO3
WRPMC PMC35
PCM3
VDD WRPM
Internal bus
P PM35
Selector
WRPORT
SO3 P35
P N
P35
Selector
RDIN INTP131
Address
Noise elimination Edge detection
Selector
PCM3
Figure 13-15. Block Diagram of P36 (Port 3)
WRPMC PMC36 VDD WRPM
Internal bus
PUO3
PM36
P
WRPORT P36
Selector
P N
P36
RDIN INTP132 SI3
Address
Noise elimination Edge detection
Selector
PCM3
Data Sheet U12261EJ2V1DS00
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PD703003
Figure 13-16. Block Diagram of P37 (Port 3)
SCK3 I/O switch
WRPMC PMC37
PCM3
PUO3
VDD WRPM
Internal bus
P PM37
Selector
WRPORT
SCK3 output P37
P N
P37
Selector
RDIN INTP133 SCK3 input
Address
Noise elimination Edge detection
Selector
PCM3
Figure 13-17. Block Diagram of P40 to P47 (Port 4)
MODE MM0 to MM2
I/O control circuit WRPM PM4n
Internal bus
Selector
WRPORT AD0 to AD7 output P4n
Selector
P4n
Address RDIN AD0 to AD7 input
Remark n = 0 to 7
40
Data Sheet U12261EJ2V1DS00
Selector
PD703003
Figure 13-18. Block Diagram of P50 to P57 (Port 5)
MODE MM0 to MM2
I/O control circuit WRPM PM5n
Internal bus
Selector
WRPORT AD8 to AD15 output P5n
Selector
P5n
Address RDIN AD8 to AD15 input
Remark n = 0 to 7 Figure 13-19. Block Diagram of P60 to P63 (Port 6)
MODE MM0 to MM2
I/O control circuit WRPM PM6n
Internal bus
A16 to A19 output P6n
Selector
WRPORT
Selector
P6n
Selector
Address RDIN
Remark n = 0 to 3
Selector
Data Sheet U12261EJ2V1DS00
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PD703003
Figure 13-20. Block Diagram of P70 to P77 (Port 7)
Internal bus
P7n
RDIN
Sample & hold circuit
ANI0 to ANI7
Remark n = 0 to 7 Figure 13-21. Block Diagram of P90 to P95 (Port 9)
MODE MM0 to MM3
I/O control circuit WRPM PM9n
Internal bus
Selector
WRPORT
LBEN, UBEN, R/W, DSTB, ASTB, HLDAK P9n
P9n
Selector
Address RDIN
Remark n = 0 to 5
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Data Sheet U12261EJ2V1DS00
Selector
PD703003
Figure 13-22. Block Diagram of P96 (Port 9)
MM3
I/O control circuit WRPM PM96
Internal bus
WRPORT P96 P96
Selector
Address RDIN HLDRQ
Figure 13-23. Block Diagram of P110 and P111 (Port 11)
WRPMC PMC11n WRPM PM11n
Internal bus
WRPORT
TO14n P11n
Selector
Selector
P11n
Selector
RDIN
Address
Remark n = 0, 1
Selector
Data Sheet U12261EJ2V1DS00
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PD703003
Figure 13-24. Block Diagram of P112 to P117 (Port 11)
WRPMC PMC11n WRPM PM11n Internal bus
WRPORT P11n Selector P11n
RDIN TCLR14, TI14 INTP140 to INTP143
Address
Noise elimination Edge detection
Remark n = 2 to 7
44
Data Sheet U12261EJ2V1DS00
Selector
PD703003
14. RESET FUNCTIONS
When low-level input occurs at the RESET pin, a system reset is performed and the various on-chip hardware devices are reset to their initial settings. When the input at the RESET pin changes from low level to high level, the reset status is canceled and the CPU resumes program execution. The contents of the various registers should be initialized within the program as necessary. The feature of the reset functions is shown below. * On-chip noise elimination circuit which uses analog delay ( 60 ns) for the RESET pin
Data Sheet U12261EJ2V1DS00
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PD703003
15. INSTRUCTION SET
* How to read instruction set tables
Indicates the instruction group. Instructions are listed in these table according to their respective groups.
Indicates the mnemonic abbreviation for the instruction.
Indicates the instruction's operands (see Table 15-1).
Indicates the instruction binary code. The binary codes for 32-bit instructions are shown in two levels (see Table 15-2).
Indicates instruction operation (see Table 15-3).
Indicates flag operations (see Table 15-4).
Instruction group
Flags Mnemonic Operand Opcode Operation CY OV S Z SAT
Table 15-1. Symbols Used to Indicate Operands
Symbol reg1 reg2 ep bit#3 immX dispX regID vector cccc Description General registers (r0 to r31): used as source registers General registers (r0 to r31): mainly used as destination registers Element pointer (r30) 3-bit data used to specify bit number X bits immediate X bits displaced System register number 5-bit data used to specify trap vector (00H to 1FH) 4-bit data used to indicate condition code
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Data Sheet U12261EJ2V1DS00
PD703003
Table 15-2. Symbols Used to Indicate Opcodes
Symbol R r d i cccc bbb 1-bit data of code specifying reg1 or regID 1-bit data of code specifying reg2 1 bit of displaced data 1 bit of immediate data 4-bit data used to indicate condition code 3-bit data used to specify bit number Description
Table 15-3. Symbols Used to Indicate Operations
Symbol GR [ ] SR [ ] zero-extend (n) sign-extend (n) load-memory (a, b) store-memory (a, b, c) load-memory-bit (a, b) store-memory-bit (a, b, c) saturated (n) Assign General register System register Zero-extend n up until word length Sign-extend n up until word length Read data having size b from address a Replace data b at address a with data having size c Read bit b from address a Write c to bit b from address a Execute saturation processing for n (n = complement to 2) Calculation of n: When n 7FFFFFFFH, result is 7FFFFFFFH. When n 80000000H, result is 80000000H. result Byte Halfword Word + - || x / AND OR XOR NOT logically shift left by logically shift right by arithmetically shift right by Result is indicated by flag operations Byte (8 bits) Half word (16 bits) Word (32 bits) Add Subtract Bit linkage Multiply Divide Logical AND Logical OR Exclusive OR Logical NOT Logical shift left Logical shift right Arithmetic shift right Description
Data Sheet U12261EJ2V1DS00
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PD703003
Table 15-4. Flag Operations
Identifier (Blank) 0 x R No change Clear to zero Set or clear according to result Restore previously saved value(s) Description
Table 15-5. Condition Codes
Condition name (cond) V NV C/L Condition code (cccc) 0000 1000 0001 Conditional expression OV = 1 OV = 0 CY = 1 Overflow No overflow Carry Lower (Less than) No carry No lower (Greater than or equal) Z/E 0010 Z=1 Zero Equal Not zero Not equal Not higher (Less than or equal) Higher (Greater than) Negative Positive Always (unconditional) Saturated Less than signed Greater than or equal signed Less than or equal signed Greater than signed Description
NC/NL
1001
CY = 0
NZ/NE
1010
Z=0
NH H N P T SA LT GE LE GT
0011 1011 0100 1100 0101 1101 0110 1110 0111 1111
(CY OR Z) = 1 (CY OR Z) = 0 S=1 S=0 - SAT = 1 (S XOR OV) = 1 (S XOR OV) = 0 ((S XOR OV) OR Z) = 1 ((S XOR OV) OR Z) = 0
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Data Sheet U12261EJ2V1DS00
PD703003
Instruction Set List
Instruction Mnemonic group Load/store SLD.B instructions SLD.H Operand Opcode Operation Flags CY OV S Z SAT disp7[ep], reg2 r r r r r 0 1 1 0 d d d d d d d adr ep + zero-extend (disp7) GR[reg2] sign-extend (Load-memory (adr, Byte)) r r r r r 1 0 0 0 d d d d d d d adr ep + zero-extend (disp8) Note 1 GR[reg2] sign-extend (Load-memory (adr, Halfword)) r r r r r 1 0 1 0 d d d d d d 0 adr ep + zero-extend (disp8) Note 2 GR[reg2] Load-memory (adr, Word) r r r r r 1 1 1 0 0 0 RRRRR adr GR[reg1] + sign-extend (disp16) d d d d d d d d d d d d d d d d GR[reg2] sign-extend (Load-memory (adr, Byte)) r r r r r 1 1 1 0 0 1 RRRRR adr GR[reg1] + sign-extend (disp16) d d d d d d d d d d d d d d d 0 GR[reg2] sign-extend (Load-memory (adr, Halfword)) Note 3 r r r r r 1 1 1 0 0 1 RRRRR adr GR[reg1] + sign-extend (disp16) d d d d d d d d d d d d d d d 1 GR[reg2] Load-memory (adr, Word) Note 3 r r r r r 0 1 1 1 d d d d d d d adr ep + zero-extend (disp7) Store-memory (adr, GR[reg2], Byte) r r r r r 1 0 0 1 d d d d d d d adr ep + zero-extend (disp8) Note 1 Store-memory (adr, GR[reg2], Halfword) r r r r r 1 0 1 0 d d d d d d 1 adr ep + zero-extend (disp8) Note 2 Store-memory (adr, GR[reg2], Word) r r r r r 1 1 1 0 1 0 RRRRR adr GR[reg1] + sign-extend (disp16) d d d d d d d d d d d d d d d d Store-memory (adr, GR[reg2], Byte) r r r r r 1 1 1 0 1 1 RRRRR adr GR[reg1] + sign-extend (disp16) d d d d d d d d d d d d d d d 0 Store-memory (adr, GR[reg2], Halfword) Note 3 r r r r r 1 1 1 0 1 1 RRRRR adr GR[reg1] + sign-extend (disp16) d d d d d d d d d d d d d d d 1 Store-memory (adr, GR[reg2], Word) Note 3 r r r r r 0 0 0 0 0 0 RRRRR GR[reg2] GR[reg1] r r r r r 010000 i i i i i GR[reg2] sign-extend (imm5)
disp8[ep], reg2
SLD.W
disp8[ep], reg2
LD.B
disp16[reg1], reg2
LD.H
disp16[reg1], reg2
LD.W
disp16[reg1], reg2
SST.B
reg2, disp7[ep]
SST.H
reg2, disp8[ep]
SST.W
reg2, disp8[ep]
ST.B
reg2, disp16[reg1]
ST.H
reg2, disp16[reg1]
ST.W
reg2, disp16[reg1]
Arithmetic MOV operation MOV instructions MOVHI
reg1, reg2 imm5, reg2
imm16, reg1, reg2 r r r r r 1 1 0 0 1 0 RRRRR GR[reg2] GR[reg1] + (imm16 || 016) iiiiiiiiiiiiiiii imm16, reg1, reg2 r r r r r 1 1 0 0 0 1 RRRRR GR[reg2] GR[reg1] + sign-extend (imm16) iiiiiiiiiiiiiiii reg1, reg2 imm5, reg2 r r r r r 0 0 1 1 1 0 RRRRR GR[reg2] GR[reg2] + GR[reg1] r r r r r 010010 i i i i i GR[reg2] GR[reg2] + sign-extend (imm5) x x x x x xx xx xx xx xx x x x x x
MOVEA
ADD ADD ADDI
imm16, reg1, reg2 r r r r r 1 1 0 0 0 0 RRRRR GR[reg2] GR[reg1] + sign-extend (imm16) iiiiiiiiiiiiiiii reg1, reg2 reg1, reg2 r r r r r 0 0 1 1 0 1 RRRRR GR[reg2] GR[reg2] - GR[reg1] r r r r r 0 0 1 1 0 0 RRRRR GR[reg2] GR[reg1] - GR[reg2]
SUB SUBR
Notes 1. ddddddd = high-order 7 bits of disp8 2. dddddd = high-order 6 bits of disp8 3. ddddddddddddddd = high-order 15 bits of disp16
Data Sheet U12261EJ2V1DS00
49
PD703003
Instruction Mnemonic group Arithmetic MULH operation instructions MULH Operand Opcode Operation Flags CY OV S Z SAT reg1, reg2 r r r r r 0 0 0 1 1 1 RRRRR GR[reg2] r r r r r 010111 i i i i i GR[reg2] GR[reg2]Note GR[reg2]Note x GR[reg1]Note (signed multiplication) imm5, reg2 x sign-extend (imm5) (signed multiplication)
MULHI
imm16, reg1, reg2 r r r r r 1 1 0 1 1 1 RRRRR GR[reg2] GR[reg1] Note x imm16 iiiiiiiiiiiiiiii (signed multiplication) reg1, reg2 reg1, reg2 imm5, reg2 cccc, reg2 r r r r r 0 0 0 0 1 0 RRRRR GR[reg2] GR[reg2] / GR[reg1] Note (signed division) r r r r r 0 0 1 1 1 1 RRRRR result GR[reg2] - GR[reg1] r r r r r 010011 i i i i i result GR[reg2] - sign-extend (imm5) x x xx xx xx x x x
DIVH CMP CMP SETF
r r r r r 1 1 1 1 1 1 0 c c c c if conditions are satisfied 0000000000000000 then GR[reg2] 00000001H else GR[reg2] 00000000H r r r r r 0 0 0 1 1 0 RRRRR GR[reg2] saturated (GR[reg2] + GR[reg1]) r r r r r 010001 i i i i i GR[reg2] saturated (GR[reg2] + sign-extend (imm5)) x x x xx xx xx xx xx 0x 0x 0x 0x x x x x x x x x x x x x x x
Saturated SATADD reg1, reg2 operation SATADD imm5, reg2 instructions SATSUB reg1, reg2
r r r r r 0 0 0 1 0 1 RRRRR GR[reg2] saturated (GR[reg2] - GR[reg1])
SATSUBI imm16, reg1, reg2 r r r r r 1 1 0 0 1 1 RRRRR GR[reg2] saturated (GR[reg1] - sign-extend (imm16)) x iiiiiiiiiiiiiiii SATSUBR reg1, reg2 Logical TST operation OR instruction ORI reg1, reg2 reg1, reg2 r r r r r 0 0 0 1 0 0 RRRRR GR[reg2] saturated (GR[reg1] - GR[reg2]) r r r r r 0 0 1 0 1 1 RRRRR result GR[reg2]AND GR[reg1] r r r r r 0 0 1 0 0 0 RRRRR GR[reg2] GR[reg2]OR GR[reg1] x
imm16, reg1, reg2 r r r r r 1 1 0 1 0 0 RRRRR GR[reg2] GR[reg1]OR zero-extend (imm16) iiiiiiiiiiiiiiii reg1, reg2 r r r r r 0 0 1 0 1 0 RRRRR GR[reg2] GR[reg2]AND GR[reg1]
AND ANDI
imm16, reg1, reg2 r r r r r 1 1 0 1 1 0 RRRRR GR[reg2] GR[reg1]AND zero-extend (imm16) iiiiiiiiiiiiiiii reg1, reg2 r r r r r 0 0 1 0 0 1 RRRRR GR[reg2] GR[reg2]XOR GR[reg1]
00x 0x 0x 0x x 0x 0x 0x 0x 0x 0x x x x x x x x x x
XOR XORI
imm16, reg1, reg2 r r r r r 1 1 0 1 0 1 RRRRR GR[reg2] GR[reg1]XOR zero-extend (imm16) iiiiiiiiiiiiiiii reg1, reg2 reg1, reg2 r r r r r 0 0 0 0 1 RRRRR GR[reg2] NOT (GR[reg1])
NOT SHL
r r r r r 1 1 1 1 1 1 RRRRR GR[reg2] GR[reg2]logically shift left by GR[reg1] 0000000011000000 r r r r r 010110 i i i i i
SHL
imm5, reg2
GR[reg2] GR[reg2]logically shift left by x zero-extend (imm5)
SHR
reg1, reg2
r r r r r 1 1 1 1 1 1 RRRRR GR[reg2] GR[reg2]logically shift right by GR[reg1] x 0000000010000000 r r r r r 010100 i i i i i GR[reg2] GR[reg2]logically shift right by x zero-extend (imm5)
SHR
imm5, reg2
SAR
reg1, reg2
r r r r r 1 1 1 1 1 1 RRRRR GR[reg2] GR[reg2]arithmetically shift right by x 0000000010100000 GR[reg1] r r r r r 010101 i i i i i GR[reg2] GR[reg2]arithmetically shift right by x zero-extend (imm5)
SAR
imm5, reg2
Note Only the low-order half word is valid.
50
Data Sheet U12261EJ2V1DS00
PD703003
Instruction Mnemonic group Branch JMP instructions JR Operand Opcode Operation Flags CY OV S Z SAT [reg1] disp22 0 0 0 0 0 0 0 0 0 1 1 RRRRR PC GR[reg1] 0 0 0 0 0 1 1 1 1 0 d d d d d d PC PC + sign-extend (disp22) ddddddddddddddd0 Note 1 r r r r r 1 1 1 1 0 d d d d d d GR[reg2] PC + 4 d d d d d d d d d d d d d d d 0 PC PC + sign-extend (disp22) Note 1 d d d d d 1 0 1 1 d d d c c c c if conditions are satisfied Note 2 then PC PC + sign-extend (disp9) x
JARL
disp22, reg2
Bcond
disp9
Bit SET1 manipulation instructions CLR1
bit#3, disp16[reg1] 0 0 b b b 1 1 1 1 1 0 RRRRR adr GR[reg1] + sign-extend (disp16) d d d d d d d d d d d d d d d d Z flag Not (Load-memory-bit (adr, bit#3)) Store-memory-bit (adr, bit#3, 1) bit#3, disp16[reg1] 1 0 b b b 1 1 1 1 1 0 RRRRR adr GR[reg1] + sign-extend (disp16) d d d d d d d d d d d d d d d d Z flag Not (Load-memory-bit (adr, bit#3)) Store-memory-bit (adr, bit#3, 0) bit#3, disp16[reg1] 0 1 b b b 1 1 1 1 1 0 RRRRR adr GR[reg1] + sign-extend (disp16) d d d d d d d d d d d d d d d d Z flag Not (Load-memory-bit (adr, bit#3)) Store-memory-bit (adr, bit#3, Z flag) bit#3, disp16[reg1] 1 1 b b b 1 1 1 1 1 0 RRRRR adr GR[reg1] + sign-extend (disp16) d d d d d d d d d d d d d d d d Z flag Not (Load-memory-bit (adr, bit#3))
x
NOT1
x
TST1
x
Notes 1. ddddddddddddddddddddd = high-order 21 bits of disp22 2. dddddddd = high-order 8 bits of disp9
Data Sheet U12261EJ2V1DS00
51
PD703003
Instruction Mnemonic group Special instructions LDSR Operand Opcode Operation Flags CY OV S Z SAT reg2, regID r r r r r 1 1 1 1 1 1 RRRRR SR[regID] GR[reg2] 0000000000100000 Note STSR regID, reg2 r r r r r 1 1 1 1 1 1 RRRRR GR[reg2] SR[regID] 0000000001000000 0 0 0 0 0 1 1 1 1 1 1 i i i i i EIPC PC + 4 (restored PC) 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 EIPSW PSW ECR.EICC Interrupt code PSW.EP 1 PSW.ID 1 PC 00000040H (when vector is 00H to 0FH) 00000050H (when vector is 10H to 1FH) 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 if PSW.EP = 1 0000000101000000 then PC EIPC PSW EIPSW else if PSW.NP = 1 then PC FEPC PSW FEPSW else PC EIPC PSW EIPSW 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 Stops 0000000100100000 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 PSW.ID 1 0 0 0 0 0 0 0 1 0 1 1 0 0 0 0 0 (maskable interrupt prohibit) 1 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 PSW.ID 0 0 0 0 0 0 0 0 1 0 1 1 0 0 0 0 0 (maskable interrupt enable) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 No operation, uses at least one clock R RRRR regID = EIPC, FEPC regID = EIPSW, FEPSW regID = PSW x xx x x
TRAP
vector
RETI
HALT
DI
EI
NOP
Note In this instructions, "reg2" is the mnemonic abbreviation for the source register, but the reg1 field is used for the opcode. Consequently, these instructions differ from other instructions in a way registers are specified in mnemonics description and opcodes. rrrrr = regID specification RRRRR = reg2 specification
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Data Sheet U12261EJ2V1DS00
PD703003
16. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (TA = 25C)
Parameter Power supply voltage Symbol VDD CVDD CVSS AVDD AVSS Input voltage Clock input voltage Low-level output current VI1 VK IOL VDD pin CVDD pin CVSS pin AVDD pin AVSS pin Note, VDD = 5.0 V 10 % X1 pin, VDD = 5.0 V 10 % 1 pin Total for all pins High-level output current IOH 1 pin Total for all pins Output voltage Analog input voltage VO VIAN VDD = 5.0 V 10 % P70/ANI0 to P77/ANI7 AVDD > VDD VDD AVDD Analog reference input voltage AVREF AVREF1 to AVREF3 AVDD > VDD VDD AVDD Operating temperature Storage temperature TA Tstg Condition Rating -0.5 to +7.0 -0.5 to VDD + 0.3 -0.5 to +0.5 -0.5 to VDD + 0.3 -0.5 to +0.5 -0.5 to VDD + 0.3 -0.5 to VDD + 1.0 4.0 100 -4.0 -100 -0.5 to VDD + 0.3 -0.5 to VDD + 0.3 -0.5 to AVDD + 0.3 -0.5 to VDD + 0.3 -0.5 to AVDD + 0.3 -40 to +85 -65 to +150 Units V V V V V V V mA mA mA mA V V V V V C C
Note X1, P70/ANI0 to P77/ANI7, and AVREF1 to AVREF3 are excluded. Cautions 1. Be sure to avoid direct connections among the IC device output (or I/O) pins and between VDD or VCC and GND. However, open-drain pins and open collector pins can be directly connected. A direct connection to an external circuit can be made to avoid conflicting output from high-impedance pins if the external circuit is designed for the correct timing. 2. If the absolute maximum rating for any of the above parameters is exceeded even momentarily, it may adversely affect the quality of this product. In other words, these absolute maximum ratings have been set to prevent physical damage to the product. Do not use the product in such a way as to exceed any of these ratings. The ratings and conditions shown below for DC characteristics and AC characteristics are within the range for normal operation and quality assurance. Capacitance (TA = 25C, VDD = VSS = 0 V)
Parameter Input capacitance I/O capacitance Output capacitance Symbol CI CIO CO Condition fC = 1 MHz All pins are 0 V except for testing pin. MIN. TYP. MAX. 15 15 15 Units pF pF pF
Data Sheet U12261EJ2V1DS00
53
PD703003
Recommended Operating Conditions
Operation Mode Direct mode Internal Operating Clock Frequency () 0 to 33 MHzNote 1 5 to 33 PLL mode MHzNote 2 Operating Ambient Temperature (TA) -40 to +85C -40 to +85C -40 to +85C Power Supply Voltage (VDD) 5.0 V 10% 5.0 V 10% 5.0 V 10%
Free-running oscillation frequency to 33 MHz
Notes 1. When not using A/D converter 2. When using A/D converter Remark The range of internal operating clock frequency in PLL mode is the assured range of function operation. PLL locked frequency is specified by tCYX. Recommended Oscillator (a) Ceramic oscillation resonator connection (TA = -40 to +85C)
X1
X2
C1
C2
Oscillation Manufacturer Part Number Frequency fXX (MHz) TDK CCR5.0MC3 FCR5.0MC5 CCR6.6MC3 Murata Mfg. CSA5.00MG040 CST5.00MGW040 CSA6.60MTZ040 CST6.60MTW040 5.0 5.0 6.6 5.0 5.0 6.6 6.6
Recommended Circuit Constant C1 (pF) On-chip On-chip On-chip 100 On-chip 100 On-chip C2 (pF) On-chip On-chip On-chip 100 On-chip 100 On-chip
Oscillation Voltage Oscillation Stabilization Range Time (MAX.) MIN. (V) MAX. (V) 4.5 4.5 4.5 4.5 4.5 4.5 4.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 TOST (ms) 0.36 0.32 0.28 0.46 0.46 0.42 0.42
Cautions 1. Set the oscillator as close to the X1 and X2 pins as possible. 2. No other signal lines should be wired in the area enclosed by broken lines. 3. When matching PD703003 with a resonator, be sure to perform sufficient evaluation.
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Data Sheet U12261EJ2V1DS00
PD703003
(b) External clock input
X1
X2 Open
High-speed CMOS inverter External clock
Cautions 1. Set high-speed CMOS inverter as close as possible to the X1 pin. 2. When matching PD703003 and a high-speed CMOS inverter, be sure to perform sufficient evaluation.
Data Sheet U12261EJ2V1DS00
55
PD703003
DC Characteristics (TA = -40 to +85C, VDD = 5.0 V 10%, VSS = 0 V)
Parameter High-level input voltage Symbol VIH Condition Except for X1 and pins listed in Note Note Low-level input voltage VIL Except for X1 and pins listed in Note Note High-level clock input voltage Low-level clock input voltage Schmitt trigger input Threshold voltage Schmitt trigger input hysteresis width High-level output voltage VXH VXL VT+ VT- X1 X1 Note, rising edge Note, falling edge 0.5 0.7 VDD VDD - 0.5 0.45 10 -10 10 -10 15 40 90 MIN. 2.2 0.8 VDD -0.5 -0.5 0.8 VDD -0.5 3.0 2.0 TYP. MAX. VDD + 0.3 VDD + 0.3 +0.8 0.2 VDD VDD + 0.5 +0.6
(1/2)
Units V V V V V V V V V V V V
VT+ - VT- Note VOH IOH = -2.5 mA IOH = -100 A
Low-level output voltage High-level input leak current Low-level input leak current High-level output leak current Low-level output leak current Software pull-up resistance
VOL ILIH ILIL ILOH ILOL R
IOL = 2.5 mA VI = VDD VI = 0 V VO = VDD VO = 0 V P35/INTP131/SO3, P36/INTP132/SI3, P37/INTP133/SCK3
A A A A
k
Note P02/TCLR11, P03/TI11, P04/INTP110 to P07/INTP113, P12/TCLR12, P13/TI12, P14/INTP120, P15/ INTP121/SO2, P16/INTP122/SI2, P17/INTP123/SCK2, P23/RXD0/SI0, P24/SCK0, P26/RXD1/SI1, P27/SCK1, P32/TCLR32, P33/TI13, P34/INTP130, P35/INTP131/SO3, P36/INTP132/SI3, P37/INTP133/ SCK3, P112/TCLR14, P113/TI14, P114/INTP140 to P117/INTP143, RESET, NMI, MODE Remarks 1. TYP. values are reference values for when TA = 25C and VDD = 5.0 V. 2. = Internal system clock frequency
56
Data Sheet U12261EJ2V1DS00
PD703003
DC Characteristics (TA = -40 to +85C, VDD = 5.0 V 10%, VSS = 0 V)
Parameter Power supply current When operating Symbol IDD1 Condition Direct modeNote PLL mode Direct modeNote MIN. TYP. MAX. 2.4 x + 6 2.8 x + 19 2.5 x + 8 2.9 x + 22 1.4 x + 5 1.5 x + 18 1.5 x + 7 1.6 x + 20 18.6 x + 100 22 x + 200 0.05 x + 4 0.1 x + 8 2 2 50 200
(2/2)
Units mA mA mA mA
During IDD2 HALT mode During IDLE mode IDD3
PLL mode Direct modeNote PLL mode -40C TA +50C 50C < TA 85C
A
mA
During IDD4 STOP mode
A A
Note When using A/D converter: = 5 to 33 MHz When not using A/D converter: = 0 to 33 MHz Remarks 1. TYP. values are reference values for when TA = 25C and VDD = 5.0 V. The power supply current does not include AVREF1 to AVREF3 or the current that flows across the software pull-up resistance. 2. = Internal system clock frequency
Data Sheet U12261EJ2V1DS00
57
PD703003
Data Hold Characteristics (TA = -40 to +85C)
Parameter Data hold voltage Data hold current Symbol VDDDR IDDDR STOP mode VDD = VDDDR -40C TA +50C 50C < TA 85C Power supply voltage rise time Power supply voltage fall time Power supply voltage hold time (vs. STOP mode setting) tRVD tFVD tHVD 200 200 0 0 Note Note 0.9 VDDDR 0 VDDDR 0.1 VDDDR Conditions MIN. 1.5 0.2 VDDDR 0.2 VDDDR TYP. MAX. 5.5 50 200 Units V
A A s s
ms ns V V
STOP mode release signal input time tDREL Data hold high-level input voltage Data hold low-level input voltage VIHDR VILDR
Note P02/TCLR11, P03/TI11, P04/INTP110 to P07/INTP113, P12/TCLR12, P13/TI12, P14/INTP120, P15/ INTP121/SO2, P16/INTP122/SI2, P17/INTP123/SCK2, P23/RXD0/SI0, P24/SCK0, P26/RXD1/SI1, P27/SCK1, P32/TCLR32, P33/TI13, P34/INTP130, P35/INTP131/SO3, P36/INTP132/SI3, P37/INTP133/ SCK3, P112/TCLR14, P113/TI14, P114/INTP140 to P117/INTP143, RESET, NMI, MODE, X1 Remark TYP. values are reference values for when TA = 25C and VDD = 5.0 V.
STOP mode setting (fifth clock after PSC register is set) VDD VDD tHVD tFVD VDDDR tRVD tDREL VDD
RESET (input)
VIHDR
NMI (input) (Released at falling edge)
VIHDR
NMI (input) (Released at rising edge) VILDR
58
Data Sheet U12261EJ2V1DS00
PD703003
AC Characteristics (TA = -40 to +85C, VDD = 5 V 10%, VSS = 0 V) AC test input waveform (a) P02/TCLR11, P03/TI11, P04/INTP110 to P07/INTP113, P12/TCLR12, P13/TI12, P14/INTP120, P15/INTP121/ SO2, P16/INTP122/SI2, P17/INTP123/SCK2, P23/RXD0/SI0, P24/SCK0, P26/RXD1/SI1, P27/SCK1, P32/ TCLR32, P33/TI13, P34/INTP130, P35/INTP131/SO3, P36/INTP132/SI3, P37/INTP133/SCK3, P112/TCLR14, P113/TI14, P114/INTP140 to P117/INTP143, RESET, NMI, MODE, X1
VDD
0.8 VDD Test points 0.2 VDD
0.8 VDD 0.2 VDD
0V
(b) Pins other than those listed in (a) above
2.4 V
2.2 V Test points 0.8 V
2.2 V 0.8 V
0.4 V
AC test output test points
2.2 V Test points 0.8 V
2.2 V 0.8 V
Load condition
DUT (Device Under Testing) CL = 50 pF
Caution
In cases where the load capacitance is greater than 50 pF due to the circuit configuration, insert a buffer or other element to reduce the device's load capacitance to below 50 pF.
Data Sheet U12261EJ2V1DS00
59
PD703003
(1) Clock timing
Parameter Symbol Conditions 25-MHz Version MIN. X1 input cycle <1> tCYX Direct mode PLL mode (PLL locked) X1 input high-level width <2> tWXH Direct mode PLL mode X1 input low-level width <3> tWXL Direct mode PLL mode X1 input rise time <4> tXR Direct mode PLL mode X1 input fall time <5> tXF Direct mode PLL mode CPU operating frequency -- 20 200 7 80 7 80 7 15 7 15 Note 2 Note 3 40 0.5T - 5 0.5T - 5 5 5 Direct mode 3 17 3 25 25 Note 4 Note 2 Note 3 30 0.5T - 5 0.5T - 5 5 5 17 MAX. Note 1 250 33-MHz Version MIN. 15 150 6 60 6 60 7 10 7 10 33 33 Note 4 MAX. Note 1 250 ns ns ns ns ns ns ns ns ns ns MHz MHz ns ns ns ns ns ns Units
Direct mode PLL mode
CLKOUT output cycle CLKOUT input high-level width CLKOUT input low-level width CLKOUT input rise time CLKOUT input fall time X1 CLKOUT delay time
<6> <7> <8> <9>
tCYK tWKH tWKL tKR
<10> tKF <11> tDXK
Notes 1. When using A/D converter When not using A/D converter 2. When using A/D converter When not using A/D converter 3. Free-running oscillation frequency 4. When using A/D converter When not using A/D converter Remark T = tCYK
Parameter Free-running oscillation frequency Symbol --
: 100 ns : DC : 5 MHz : 0 MHz : 200 ns : DC
Conditions PLL mode
TYP. 5
Units MHz
P
<1> <2> X1 (input) <3>
<4> <11> CLKOUT (output) <11>
<5> <7>
<6> <8>
<9>
<10>
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Data Sheet U12261EJ2V1DS00
PD703003
(2) Input waveform (a) P02/TCLR11, P03/TI11, P04/INTP110 to P07/INTP113, P12/TCLR12, P13/TI12, P14/INTP120, P15/ INTP121/SO2, P16/INTP122/SI2, P17/INTP123/SCK2, P23/RXD0/SI0, P24/SCK0, P26/RXD1/SI1, P27/ SCK1, P32/TCLR32, P33/TI13, P34/INTP130, P35/INTP131/SO3, P36/INTP132/SI3, P37/INTP133/ SCK3, P112/TCLR14, P113/TI14, P114/INTP140 to P117/INTP143, RESET, NMI, MODE
Parameter Symbol Conditions 25-MHz Version MIN. Input rise time Input fall time <12> tIR2 <13> tIF2 MAX. 20 20 33-MHz Version MIN. MAX. 20 20 ns ns Units
VDD Input signal 0V
0.8 VDD 0.2 VDD <13> 0.2 VDD
0.8 VDD
<12>
(b) Pins other than those listed in (a) above
Parameter Symbol Conditions 25-MHz Version MIN. Input rise time Input fall time <14> tIR1 <15> tIF1 MAX. 10 10 33-MHz Version MIN. MAX. 10 10 ns ns Units
2.4 V Input signal 0.4 V
2.2 V 0.8 V <15> 0.8 V
2.2 V
<14>
Data Sheet U12261EJ2V1DS00
61
PD703003
(3) Output waveform (other than CLKOUT)
Parameter Symbol Conditions 25-MHz Version MIN. Output rise time Output fall time <16> tOR <17> tOF MAX. 12 12 33-MHz Version MIN. MAX. 12 12 ns ns Units
2.2 V Output signal 0.8 V <16>
2.2 V 0.8 V <17>
(4) Reset timing
Parameter Symbol Conditions 25-MHz Version MIN. RESET high-level width RESET low-level width <18> tWRSH <19> tWRSL When power supply is ON and STOP mode has been released Other than when power supply is ON and STOP mode has been released 500 500 + TOST MAX. 33-MHz Version MIN. 500 500 + TOST MAX. ns ns Units
500
500
ns
Remark TOST: Oscillation stabilization time
<18>
<19>
RESET (input)
62
Data Sheet U12261EJ2V1DS00
PD703003
[MEMO]
Data Sheet U12261EJ2V1DS00
63
PD703003
(5) Read timing (1/2)
Parameter Symbol Conditions 25-MHz Version MIN. CLKOUT address delay time <20> tDKA CLKOUT R/W, UBEN, LBEN delay time <78> tDKA2 CLKOUT address float delay time <21> tFKA CLKOUT ASTB delay time CLKOUT DSTB delay time <22> tDKST <23> tDKD 3 -2 3 -2 -2 7 5 8 5 0 0.5T - 10 0.5T - 10 0 (2 + n)T - 20 (1 + n)T - 20 0.5T - 10 0 (1 + i)T - 3 0.5T - 10 (1.5 + i)T - 10 (1 + n)T - 10 T - 10 n1 n1 n1 n1 1.5T - 20 (1.5 + n)T - 20 (0.5 + n)T (1.5 + n)T T - 15 (1 + n)T - 15 nT (1 + n)T nT (1 + n)T (0.5 + n)T (1.5 + n)T T - 15 (1 + n)T - 15 0.5T - 10 0 (1 + i)T - 3 0.5T - 10 (1.5 + i)T - 10 (1 + n)T - 10 T - 10 1.5T - 20 (1.5 + n)T - 20 MAX. 20 +13 15 +13 +13 33-MHz Version MIN. 3 -2 3 -2 -2 7 5 8 5 0 0.5T - 10 0.5T - 10 0 (2 + n)T - 20 (1 + n)T - 20 MAX. 20 +13 15 +13 +13 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Units
Data input setup time (to CLKOUT) <24> tSIDK Data input hold time (from CLKOUT) <25> tHKID WAIT setup time (to CLKOUT) <26> tSWTK WAIT hold time (from CLKOUT) <27> tHKWT Address hold time (from CLKOUT) <28> tHKA Address setup time (to ASTB) <29> tSAST
Address hold time (from ASTB) <30> tHSTA DSTB address float delay time <31> tFDA Data input setup time (to address) <32> tSAID Data input setup time (to DSTB) <33> tSDID ASTB DSTB delay time <34> tDSTD
Data input hold time (from DSTB) <35> tHDID DSTB address output delay time <36> tDDA DSTB ASTB delay time DSTB ASTB delay time DSTB low-level width ASTB high-level width WAIT setup time (to address) <37> tDDSTH <38> tDDSTL <39> tWDL <40> tWSTH <41> tSAWT1 <42> tSAWT2 WAIT hold time (from address) <43> tHAWT1 <44> tHAWT2 WAIT setup time (to ASTB) <45> tSSTWT1 <46> tSSTWT2 WAIT hold time (from ASTB) <47> tHSTWT1 <48> tHSTWT2
Remarks 1. T = tCYK 2. n indicates the number of wait clocks that are inserted during a bus cycle. The sampling timing may vary when using the programmable wait insertion function. 3. i indicates the number of idle states (0 or 1) that are inserted after a read cycle. 4. Maintain at least one of the two data input hold times, either tHKID (<25>) or tHDID (<35>).
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Data Sheet U12261EJ2V1DS00
PD703003
(5) Read timing (2/2): 1 wait
T1 T2 TW T3
CLKOUT (output)
<20>
<28>
A16 to A19 (output)
<78>
R/W (output) UBEN (output) LBEN (output)
<32> <21> <24> <25>
AD0 to AD15 (I/O)
A0 to A15 (output)
<22> <29> <30>
D0 to D15 (input)
<35> <22>
ASTB (output)
<37> <33> <23> <36>
<40>
<34> <31> <23>
DSTB (output)
<38> <39>
<45> <26> <47>
<27>
<26>
<27>
<46> <48>
WAIT (input)
<41> <43> <42> <44>
Remark Broken line indicates high impedance.
Data Sheet U12261EJ2V1DS00
65
PD703003
(6) Write timing (1/2)
Parameter Symbol Conditions 25-MHz Version MIN. CLKOUT address delay time <20> tDKA CLKOUT R/W, UBEN, LBEN delay time <78> tDKA2 CLKOUT ASTB delay time CLKOUT DSTB delay time <22> tDKST <23> tDKD 3 -2 -2 -2 8 5 0 0.5T - 10 0.5T - 10 0.5T - 10 0.5T - 10 (1 + n)T - 10 T - 10 n1 n1 n1 n1 1.5T - 20 (1.5 + n)T - 20 (0.5 + n)T (1.5 + n)T T - 15 (1 + n)T - 15 nT (1 + n)T 20 10 0 (1 + n)T - 15 T - 10 0 (1 + n)T - 15 T - 10 nT (1 + n)T 20 10 (0.5 + n)T (1.5 + n)T T - 15 (1 + n)T - 15 MAX. 20 +13 +13 +13 33-MHz Version MIN. 3 -2 -2 -2 8 5 0 0.5T - 10 0.5T - 10 0.5T - 10 0.5T - 10 (1 + n)T - 10 T - 10 1.5T - 20 (1.5 + n)T - 20 MAX. 20 +13 +13 +13 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Units
WAIT setup time (to CLKOUT) <26> tSWTK WAIT hold time (from CLKOUT) <27> tHKWT Address hold time (from CLKOUT) <28> tHKA Address setup time (to ASTB) <29> tSAST
Address hold time (from ASTB) <30> tHSTA ASTB DSTB delay time DSTB ASTB delay time DSTB low-level width ASTB high-level width WAIT setup time (to address) <34> tDSTD <37> tDDSTH <39> tWDL <40> tWSTH <41> tSAWT1 <42> tSAWT2 WAIT hold time (from address) <43> tHAWT1 <44> tHAWT2 WAIT setup time (to ASTB) <45> tSSTWT1 <46> tSSTWT2 WAIT hold time (from ASTB) <47> tHSTWT1 <48> tHSTWT2 CLKOUT data output delay time <49> tDKOD DSTB data output delay time <50> tDDOD Data output hold time (from CLKOUT) <51> tHKOD Data output setup time (to DSTB) <52> tSODD Data output hold time (from DSTB) <53> tHDOD
Remarks 1. T = tCYK 2. n indicates the number of wait clocks that are inserted during a bus cycle. The sampling timing may vary when using the programmable wait insertion function.
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Data Sheet U12261EJ2V1DS00
PD703003
(6) Write timing (2/2): 1 wait
T1 T2 TW T3
CLKOUT (output)
<20>
<28>
A16 to A19 (output)
<78>
R/W (output) UBEN (output) LBEN (output)
<49>
<51>
AD0 to AD15 (I/O)
A0 to A15 (output)
<22> <29> <30>
D0 to D15 (output)
<22>
ASTB (output)
<23> <34> <50> <52> <23> <37> <53>
<40>
DSTB (output)
<39>
<45> <26> <47>
<27>
<26>
<27>
<46> <48>
WAIT (input)
<41> <43> <42> <44>
Remark Broken line indicates high impedance.
Data Sheet U12261EJ2V1DS00
67
PD703003
(7) Bus hold timing (1/2)
Parameter Symbol Conditions 25-MHz Version MIN. HLDRQ setup time (to CLKOUT) <54> tSHQK HLDRQ hold time (from CLKOUT) <55> tHKHQ CLKOUT HLDAK delay time <56> tDKHA HLDRQ high-level width HLDAK low-level width <57> tWHQH <58> tWHAL T + 10 T - 10 20 -3 (2n + 7.5)T + 20 0.5T 1.5T + 20 0.5T -3 (2n + 7.5)T + 20 1.5T + 20 8 5 20 T + 10 T - 10 20 MAX. 33-MHz Version MIN. 8 5 20 MAX. ns ns ns ns ns ns ns ns ns Units
CLKOUT bus float delay time <59> tDKF HLDAK bus output delay time <60> tDHAC HLDRQ HLDAK delay time <61> tDHQHA1 HLDRQ HLDAK delay time <62> tDHQHA2
Remarks 1. T = tCYK 2. n indicates the number of wait clocks that are inserted during a bus cycle. The sampling timing may vary when using the programmable wait insertion function.
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Data Sheet U12261EJ2V1DS00
PD703003
(7) Bus hold timing (2/2)
TH
TH
TH
TH
TI
CLKOUT (output)
<54> <54><55> <57>
HLDRQ (input)
<56> <61> <62>
<56>
HLDAK (output)
<58> <60> <59>
A16 to A19 (output)Note
AD0 to AD15 (I/O)
D0 to D15 (input or output)
ASTB (output)
DSTB (output)
R/W (output)
Note UBEN (output), LBEN (output) Remark Broken line indicates high impedance.
Data Sheet U12261EJ2V1DS00
69
PD703003
(8) Interrupt timing
Parameter Symbol Conditions 25-MHz Version MIN. NMI high-level width NMI low-level width INTPn high-level width INTPn low-level width <63> tWNIH <64> tWNIL <65> tWITH <66> tWITL n = 110 to 113, 120 to 123, 130 to 133, 140 to 143 n = 110 to 113, 120 to 123, 130 to 133, 140 to 143 500 500 3T + 10 3T + 10 MAX. 33-MHz Version MIN. 500 500 3T + 10 3T + 10 MAX. ns ns ns ns Units
Remark T = tCYK
<63> <64>
NMI (input)
<65>
<66>
INTPn (input)
Remark n = 110 to 113, 120 to 123, 130 to 133, 140 to 143
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Data Sheet U12261EJ2V1DS00
PD703003
[MEMO]
Data Sheet U12261EJ2V1DS00
71
PD703003
(9) CSI timing (1/2) (a) Master mode (i) Timing of CSI0 to CSI2
Symbol Conditions 25-MHz Version MIN. SCKn cycle SCKn high-level width SCKn low-level width SIn setup time (to SCKn) SIn hold time (from SCKn) <67> tCYSK1 <68> tWSKH1 <69> tWSKL1 <70> tSSISK1 <71> tHSKSI1 Output Output Output 160 0.5tCYSK1 - 20 0.5tCYSK1 - 20 50 0 18 0.5tCYSK1 - 5 0.5tCYSK1 - 5 MAX. 33-MHz Version MIN. 120 0.5tCYSK1 - 20 0.5tCYSK1 - 20 50 0 18 MAX. ns ns ns ns ns ns ns Units
Parameter
SOn output delay time (to SCKn) <72> tDSKSO1 SOn output hold time (from SCKn) <73> tHSKSO1
Remark n = 0 to 2 (ii) Timing of CSI3
Parameter Symbol Conditions 25-MHz Version MIN. SCK3 cycle SCK3 high-level width SCK3 low-level width SI3 setup time (to SCK3) SI3 hold time (from SCK3) <67> tCYSK3 <68> tWSKH3 <69> tWSKL3 <70> tSSISK3 <71> tHSKSI3 RL = 1.5 k CL = 50 pF Output Output Output RL = 1.5 k CL = 50 pF 500 0.5tCYSK3 - 150 0.5tCYSK3 - 70 100 50 150 tWSKH3 tWSKH3 MAX. 33-MHz Version MIN. 500 0.5tCYSK3 - 150 0.5tCYSK3 - 70 100 50 150 MAX. ns ns ns ns ns ns ns Units
SO3 output delay time (to SCK3) <72> tDSKSO3 SO3 output hold time (from SCK3) <73> tHSKSO3
Remark RL and CL are the load resistance and load capacitance of the output line for SCK3 and SO3. (b) Slave mode (i) Timing of CSI0 to CSI2
Symbol Conditions 25-MHz Version MIN. SCKn cycle SCKn high-level width SCKn low-level width SIn setup time (to SCKn) SIn hold time (from SCKn) <67> tCYSK2 <68> tWSKH2 <69> tWSKL2 <70> tSSISK2 <71> tHSKSI2 Input Input Input 160 50 50 10 10 45 tWSKH2 tWSKH2 MAX. 33-MHz Version MIN. 120 30 30 10 10 45 MAX. ns ns ns ns ns ns ns Units
Parameter
SOn output delay time (to SCKn) <72> tDSKSO2 SOn output hold time (from SCKn) <73> tHSKSO2
Remark n = 0 to 2
72
Data Sheet U12261EJ2V1DS00
PD703003
(9) CSI timing (2/2) (ii) Timing of CSI3
Parameter Symbol Conditions 25-MHz Version MIN. SCK3 cycle SCK3 high-level width SCK3 low-level width SI3 setup time (to SCK3) SI3 hold time (from SCK3) <67> tCYSK4 <68> tWSKH4 <69> tWSKL4 <70> tSSISK4 <71> tHSKSI4 RL = 1.5 k CL = 50 pF Input Input Input 500 100 180 100 50 150 tWSKH4 tWSKH4 MAX. 33-MHz Version MIN. 500 100 180 100 50 150 MAX. ns ns ns ns ns ns ns Units
SO3 output delay time (to SCK3) <72> tDSKSO4 SO3 output hold time (from SCK3) <73> tHSKSO4
Remark RL is the load resistance and CL is the load capacitance of the output line for SCK3 and SO3.
<67> <69> <68>
SCKn (I/O)
<70>
<71>
SIn (Input)
Input data
<72> <73>
SOn (output)
Output data
Remarks 1. Broken line indicates high impedance. 2. n = 0 to 3
Data Sheet U12261EJ2V1DS00
73
PD703003
(10) RPU timing
Parameter Symbol Conditions 25-MHz Version MIN. TI1n high-level width TI1n low-level width TCLR1n high-level width TCLR1n low-level width <74> tWTIH <75> tWTIL <76> tWTCH <77> tWTCL 3T + 10 3T + 10 3T + 10 3T + 10 MAX. 33-MHz Version MIN. 3T + 10 3T + 10 3T + 10 3T + 10 MAX. ns ns ns ns Units
Remark T = tCYK
<74> <75>
TI1n (input)
<76>
<77>
TCLR1n (input)
Remark n = 1 to 4
74
Data Sheet U12261EJ2V1DS00
PD703003
A/D Converter Characteristics (TA = -40 to +85C, VDD = AVDD = 5 V 10%, VSS = AVSS = 0 V)
Parameter Symbol Conditions 25-MHz Version MIN. Resolution Total errorNote 1 -- -- -- Quantization error Conversion time -- tCONV 4.5 V AVREF1 AVDD 3.5 V AVREF1 AVDD Sampling time tSAMP 4.5 V AVREF1 AVDD 3.5 V AVREF1 AVDD Zero scale errorNote 1 -- -- Full scale errorNote 1 -- -- Nonlinearity errorNote 1 -- -- Analog input voltageNote 2 Reference voltage AVREF1 current AVDD power supply current VIAN AVREF1 AIREF1 AIDD 4.5 V AVREF1 AVDD 3.5 V AVREF1 AVDD 4.5 V AVREF1 AVDD 3.5 V AVREF1 AVDD 4.5 V AVREF1 AVDD 3.5 V AVREF1 AVDD -0.3 3.5 1.2 2.3 48 48 8 8 3.0 3.0 1.5 1.5 1.5 1.5 4.5 5.5 2.5 4.5 3.5 4.5 AVDD +0.3 AVDD 3.0 6.0 -0.3 3.5 1.2 2.3 4.5 V AVREF1 AVDD 3.5 V AVREF1 AVDD 10 0.55 0.7 1/2 60 60 10 10 3.0 3.0 1.5 1.5 1.5 1.5 4.5 5.5 2.5 4.5 3.5 4.5 AVDD +0.3 AVDD 3.0 6.0 TYP. MAX. 33-MHz Version MIN. 10 0.55 0.7 1/2 TYP. MAX. bit %FSR %FSR LSB tCYK tCYK tCYK tCYK LSB LSB LSB LSB LSB LSB V V mA mA Units
Notes 1. Does not include quantization error. 2. When VIAN = 0, the conversion result becomes 000H. When 0 < VIAN < AVREF1, conversion has 10-bit resolution. When AVREF1 VIAN AVDD, the conversion result becomes 3FFH.
Data Sheet U12261EJ2V1DS00
75
PD703003
D/A Converter Characteristics (TA = -40 to +85C, VDD = AVDD = 5 V 10%, VSS = AVSS = 0 V)
Parameter Symbol Conditions 25-MHz Version MIN. Resolution Total error -- -- Load condition: 2 M, 30 pF AVREF2 = VDD AVREF3 = 0 Load condition: 2 M, 30 pF AVREF2 = 0.75 VDD AVREF3 = 0.25 VDD Load condition: 4 M, 30 pF AVREF2 = VDD AVREF3 = 0 Load condition: 4 M, 30 pF AVREF2 = 0.75 VDD AVREF3 = 0.25 VDD Load condition: 2 M, 30 pF 10 0.75 VDD 0 DACS0, DACS1 = 55H 2 5 VDD 0.25 VDD 0.75 VDD 0 2 5 TYP. MAX. 8 0.8 33-MHz Version MIN. TYP. MAX. 8 0.8 bit % Units
--
1.0
1.0
%
--
0.6
0.6
%
--
0.8
0.8
%
Settling time Output resistance AVREF2 input voltage AVREF3 input voltage AVREF2 to AVREF3 resistance value
-- RO AVREF2 AVREF3 RAIREF
10 10
10
s
k
VDD 0.25 VDD
V V k
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Data Sheet U12261EJ2V1DS00
PD703003
17. PACKAGE DRAWINGS
100 PIN PLASTIC QFP (FINE PITCH) ( 14)
A B
75 76
51 50
detail of lead end S CD R Q
100 1
26 25
F G P H I
M
J K
N
NOTE 1. Controlling dimension millimeter.
S
L M
S
ITEM A B C D F G H I J K L M N P Q R S MILLIMETERS 16.00.2 14.00.2 14.00.2 16.00.2 1.0 1.0 0.22 +0.05 -0.04 0.10 0.5 (T.P.) 1.00.2 0.50.2 0.17 +0.03 -0.07 0.10 1.450.05 0.1250.075 55 1.7 MAX. INCHES 0.6300.008 0.551 +0.009 -0.008 0.551 +0.009 -0.008 0.6300.008 0.039 0.039 0.0090.002 0.004 0.020 (T.P.) 0.039 +0.009 -0.008 0.020 +0.008 -0.009 0.007 +0.001 -0.003 0.004 0.057 +0.003 -0.002 0.0050.003 55 0.067 MAX. P100GC-50-7EA-3
2. Each lead centerline is located within 0.10 mm (0.004 inch) of its true position (T.P.) at maximum material condition.
Data Sheet U12261EJ2V1DS00
77
PD703003
18. RECOMMENDED SOLDERING CONDITIONS
The PD703003 should be soldered and mounted under the following recommended conditions. For the recommended soldering conditions, refer to the document Semiconductor Device Mounting Technology Manual (C10535E). For soldering methods and conditions other than those recommended below, contact your NEC sales representative. Table 18-1. Soldering Conditions
Soldering Method Infrared reflow Soldering Conditions Package peak temperature: 235C, Reflow time: 30 seconds or below (210C or higher), Number of reflow processes: 2 max., Exposure limit: 7 daysNote (after that, prebaking is necessary at 125C for 10 hours) Package peak temperature: 215C, Reflow time: 40 seconds or below (200C or higher), Number of reflow processes: 2 max., Exposure limit: 7 daysNote (after that, prebaking is necessary at 125C for 10 hours) Pin temperature: 300C or below, Time: 3 seconds or below (per side of device) Symbol IR35-107-2
VPS
VP15-107-2
Partial heating
--
Note Exposure limit after dry-pack is opened. Storage conditions: temperature of 25C and relative humidity of 65% or less. Caution Do not use different soldering methods together (except for partial heating).
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Data Sheet U12261EJ2V1DS00
PD703003
[MEMO]
Data Sheet U12261EJ2V1DS00
79
PD703003
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS
Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS device behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices.
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.
80
Data Sheet U12261EJ2V1DS00
PD703003
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC product in your application, please contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: * Device availability * Ordering information * Product release schedule * Availability of related technical literature * Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) * Network requirements In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country.
NEC Electronics Inc. (U.S.)
Santa Clara, California Tel: 408-588-6000 800-366-9782 Fax: 408-588-6130 800-729-9288
NEC Electronics (Germany) GmbH
Benelux Office Eindhoven, The Netherlands Tel: 040-2445845 Fax: 040-2444580
NEC Electronics Hong Kong Ltd.
Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044
NEC Electronics Hong Kong Ltd. NEC Electronics (France) S.A.
Velizy-Villacoublay, France Tel: 01-30-67 58 00 Fax: 01-30-67 58 99 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411
NEC Electronics (Germany) GmbH
Duesseldorf, Germany Tel: 0211-65 03 02 Fax: 0211-65 03 490
NEC Electronics (France) S.A. NEC Electronics (UK) Ltd.
Milton Keynes, UK Tel: 01908-691-133 Fax: 01908-670-290 Spain Office Madrid, Spain Tel: 91-504-2787 Fax: 91-504-2860
NEC Electronics Singapore Pte. Ltd.
United Square, Singapore 1130 Tel: 65-253-8311 Fax: 65-250-3583
NEC Electronics Taiwan Ltd. NEC Electronics Italiana s.r.l.
Milano, Italy Tel: 02-66 75 41 Fax: 02-66 75 42 99
NEC Electronics (Germany) GmbH
Scandinavia Office Taeby, Sweden Tel: 08-63 80 820 Fax: 08-63 80 388
Taipei, Taiwan Tel: 02-2719-2377 Fax: 02-2719-5951
NEC do Brasil S.A.
Electron Devices Division Rodovia Presidente Dutra, Km 214 07210-902-Guarulhos-SP Brasil Tel: 55-11-6465-6810 Fax: 55-11-6465-6829
J99.1
Data Sheet U12261EJ2V1DS00
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PD703003
RELATED DOCUMENTS
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Note Japanese version The related documents indicated in this publication may include preliminary version. However, preliminary versions are not marked as such. V850 Family and V853 are trademarks of NEC Corporation.
The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited without governmental license, the need for which must be judged by the customer. The export or re-export of this product from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative.
* The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. * No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. * NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. * Descriptions of circuits, software, and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software, and information in the design of the customer's equipment shall be done under the full responsibility of the customer. NEC Corporation assumes no responsibility for any losses incurred by the customer or third parties arising from the use of these circuits, software, and information. * While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. * NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance.
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